This invention relates to MOSFET devices, and more specifically to a novel process and to a novel configuration for the central high conductivity region disposed beneath the gate oxide of a high power MOSFET.
High power MOSFETS having low on-resistance and high breakdown voltage are known and are shown in the above-noted copending application Ser. No. 951,310. In the above application, the source electrodes are interdigitated source regions spaced from one another by two parallel channel regions covered by a common gate. The device has exceptionally low on-resistance and has the usual advantages of a MOSFET device over a bi-polar device. The low on-resistance is obtained by virtue of a relatively highly doped conductivity region disposed beneath the gate oxide and between the two adjacent channels. The highly doped region leads to a common drain electrode. The increased conductivity of the region beneath the oxide in the path leading to the bottom drain does not adversely affect the reverse-voltage characteristics of the device. As a result, it was possible to substantially decrease the forward resistance of the MOSFET without adversely affecting any of its other desirable characteristics.
The interdigitated source structure of application Ser. No. 951,310 has a relatively low packing density, requires relatively complicated masks and has a relatively high capacitance.
The device of copending application Ser. No. 38,662 provides a high power MOSFET device with the low forward resistance of application Ser. No. 951,310 where, however, a very high packing density is available and which can be made with relatively simple masks. The device further has relatively low capacitance. Typically, the device of application Ser. No. 38,662 uses the increased conductivity region beneath the gate oxide and D-MOS fabrication techniques. However, the individual spaced source regions are polygonal in configuration and are preferably hexagonal to ensure a constant spacing along the major lengths of the sources disposed over the surface of the body. An extremely large number of small hexagonal source elements may be formed in the same surface of the semiconductor body for a given device. By way of example, 6,600 hexagonal source regions can be formed in a chip area having a dimension of about 100 by 140 mils to produce an effective channel width of about 22,000 mils, thus permitting very high current capacity for the device. A polysilicon gate is used which has a hexagonal grid-like configuration which is disposed atop an oxide layer. Each leg of the grid overlies two spaced channels which are capable of inversion by application of a voltage to the polysilicon gate. The gate structure is contacted over the upper surface of the device by symmetric, elongated gate contact fingers which ensure good contact over the full surface of the gate.
Each of the polygonal source regions is contacted by a continuous conductive source contact layer which engages the individual polygonal sources through openings in an insulation layer covering the source regions. These openings can be formed by conventional D-MOS photolithographic techniques. A source pad connection region is then provided for the source conductor and a gate pad connection region is provided for the elongated gate fingers and a drain connection region is made to the reverse surface of the semiconductor device.
A plurality of identical chips can be formed on a single semiconductor wafer and the individual elements can be separated from one another by scribing or any other suitable method after processing is completed.
The process used to form the relatively high conductivity region beneath the gate oxide has been such that the conductivity beneath the gate oxide in the region containing the relatively high concentration of impurity carriers is relatively low in laterally central regions and high in the laterally removed side regions. As the result of this non-uniform lateral distribution, the avalanche energy of the device is not optimum. Moreover, the effective lateral resistance beneath the source region and extending from the channel regions to the metal on the surface of the device and circumscribed by the source is higher than optimum. Since this resistance is relatively high, the effective bi-polar transistor formed by three alternate conductivity regions has a high gain and can turn on easily, introducing second breakdown characteristics common to a bi-polar device but normally avoided by a MOSFET device. As the region beneath the source region becomes more depleted, the problem of possible second breakdown increases. Commonly, this shorting or parallel resistance path defining parasitic base resistance cannot be reduced without varying the polysilicon gate width which would increase the on-resistance of the device.